1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory device and method thereof, and more particularly to a semiconductor memory device and methods of operating the semiconductor memory device.
2. Description of the Related Art
Conventional semiconductor memory devices have become increasingly smaller and more integrated, while a number of input/output (I/O) pins (e.g., for designating an address, transferring power or data, etc.) may tend to increase. For example, an external address may be applied to a semiconductor memory device during two clock cycles such that a number of pins sufficient to transfer the external address during a single clock cycle need not be included.
Such a system may be referred to as a Double Pumped Address (DPA) system. In contrast to the DPA system, a system where an external address may be transferred to a semiconductor memory device in a single clock or operating cycle, may be referred to as a single pumped address (SPA) system. A conventional DPA system is described with reference to FIGS. 1 to 3.
FIG. 1 illustrates timings of internal addresses in a conventional semiconductor memory device employing a DPA system.
Referring to FIG. 1, in the DPA system, an external address Ext_Add may be applied to a semiconductor memory device during two operating cycles of a clock signal CLK. That is, an address A0 may be divided into a lower address A0_L and a higher address A0_H, which may synchronize to operating cycles CLK0 and CLK1, respectively, and may be applied to the semiconductor memory device. Next, an address A1 may be divided into a lower address A1_L and a higher address A1_H, which may synchronize to operating cycles CLK2 and CLK3, respectively, and may be applied to the semiconductor memory device, and so on.
Referring to FIG. 1, a command CMD0 corresponding to the address A0 may be applied to the semiconductor memory device, and a command CMD1 corresponding to the address A1 may be applied to the semiconductor memory device. For purposes of explanation, it may be assumed that the command CMD0 is an active command, and the command CMD1 is a memory command (e.g., a read or write command).
Referring to FIG. 1, in the DPA system, a single address may be applied to the semiconductor memory device during two clock cycles as described above. A time interval between a first internal command C0 corresponding to the first command CMD0 and a second internal command C1 corresponding to the second command CMD1 may thereby be equal to two clock cycles 2TCC (e.g., an “operating cycle time”). In an example, the first command CMD0 and the second command CMD1 may be provided as successive or consecutive commands. Thus, a time interval between internal signals Int_Sig1 and Int_Sig2 shown in FIG. 2, which is described in greater detail later, may increase. The internal signals Int_Sig1 and Int_Sig2 may be used to trigger an operation corresponding to the internal commands C0 and C1, respectively, within the semiconductor memory device.
FIG. 2 illustrates timings of a time interval between internal signals in a conventional semiconductor memory device employing an SPA system.
Referring to FIG. 2, td_CMD0 may denote a delay time between first internal signal Int_Sig1 (e.g., based on or responsive to the first internal command C0), and the first internal command C0. td_CMD1 may denote a delay time between second internal signal Int_Sig2 (e.g., based on or responsive to the second internal command C1) and the second internal command C1. t_CMD01 may denote a delay time between the first internal signal Int_Sig1 based on the first internal command C0 and the second internal signal Int_Sig2 based on the second internal command C1.
Referring to FIG. 2, a magnitude of the delay time td_CMD0, td_CMD1 may be a fixed value (e.g., in a non-DPA system or SPA system), and the delay time t_CMD01 may be expressed by:t—CMD01=2tCC+td—CMD1−td—CMD0  Equation 1
Referring to Equation 1, in calculating a point that t_CMD01 is equal to zero (e.g., a “0” margin point), Equation 1 may be reduced as follows2tCC+td—CMD1−td—CMD0=0  Equation 2tCC=(td—CMD0−td—CMD1)/2  Equation 3
Thus, as shown in Equation 3, a shortest clock cycle time of a clock signal may be ‘(td_CMD0−td_CMD1)/2’. In contrast, in a DPA system, the delay time t_CMD01 may be expressed ast—CMD01=tCC+td—CMD1−td—CMD0  Equation 4
Referring to Equation 4, in calculating a “0” margin point, Equation 3 may be reduced totCC+td—CMD1−td—CMD0=0  Equation 5tCC=td—CMD0−td—CMD1  Equation 6
Thus, as shown in Equation 6, a shortest clock cycle time of a clock signal may become ‘td_CMD0−td_CMD1’. Thus, by comparing the shortest clock cycles derived based on Equation 3 (e.g., non-DPA or SPA) and Equation 6 (e.g., DPA), the shortest clock cycle time in the SPA system may be twice that of the shortest clock cycle time in the DPA system.
FIG. 3 is a block diagram schematically illustrating an internal address generating circuit of a semiconductor memory device employing a conventional DPA system having a characteristic of the timing diagram shown in FIG. 1.
Referring to FIGS. 1 and 3, the internal address generating circuit may include first to fourth flip-flops 31 to 34, a first transmission gate 35 and a first latch 36, and a second transmission gate 37 and a second latch 38. The first flip-flop 31 and the second flip-flop 32 may receive two successive external addresses, a first external address A0_L, A0_H and a second external address A1_L, A1_H. The first flip-flop 31 and the second flip-flop 32 may operate in response to a clock signal CLK.
Referring to FIGS. 1 and 3, the first flip-flop 31 may transmit the first external address A0_L, A0_H to the first transmission gate 35 and the second transmission gate 37 in a second operating cycle CLK1 of the clock signal CLK. The first and second transmission gates 35 and 37 may not be turned in a first operating cycle CLK0 of the clock signal CLK. The third flip-flop 33 may output the first external command CMD0 corresponding to the first external address A0_L, A0_H to the fourth flip-flop 34 in response to the first operating cycle CLK0 of the clock signal CLK.
Referring to FIGS. 1 and 3, the fourth flip-flop 34 may output first internal command C0 as an internal command Int_CMD in a second operating cycle CLK1 of the clock signal CLK, to turn on the first transmission gate 35 and the second transmission gate 37. Thus, the first latch 36 and the second latch 38 may output a first internal address A0 as an internal address Int_ADD in the second operating cycle CLK1 of the clock signal CLK, and may apply the first internal address A0 to a next stage circuit.
Referring to FIGS. 1 and 3, the first transmission gate 35 and the second transmission gate 37 may be turned on by the second external command CMD1 in a fourth operating cycle CLK3 of the clock signal CLK. Thus, the first latch 36 and the second latch 38 may output a second internal address A1 as an internal address Int_ADD, and may apply the second internal address A1 to a next stage circuit.
Returning to FIG. 2, a time interval between the first external command CMD0 and the second external command CMD1 may correspond to two operating cycles. A time interval between the first internal command C0 and the second internal command C1, which may be internal commands corresponding to the external commands CMD0 and CMD1, may also correspond to two operating cycles 2tCC.
Referring to Equations 1 through 6, a margin between internal signals for two successive commands may be higher in a semiconductor memory device employing the DPA system. The margin between internal signals for two successive commands may be reduced by reducing an operating cycle time tCC of the clock signal CLK. A higher performance tester may be used to reduce the operating cycle time tCC. However, higher performance testers may typically be expensive. Thus, a semiconductor memory device employing a DPA system with cheaper, lower performance testers may have a relatively limited internal margin between commands.
Furthermore, measurements of parameters, such as AC parameters (e.g., tRCD, tRP, etc.) in a semiconductor memory device conforming to the DPA system, may be difficult if a shortest operating cycle time tCC of a tester is above a threshold. Thereby, it may be difficult to deploy lower performance testers (e.g., which may be cheaper) because lower performance testers may be associated with higher shortest operating cycle times tCC.